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- W2149118524 abstract "We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete their routing and to minimize the I/O pins used. We also describe a heuristic method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the average reduction of the I/O pins used are up to 18% compared to the previous method for all the benchmark circuits tested." @default.
- W2149118524 created "2016-06-24" @default.
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- W2149118524 date "2003-01-20" @default.
- W2149118524 modified "2023-09-24" @default.
- W2149118524 title "Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards" @default.
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- W2149118524 doi "https://doi.org/10.1109/cicc.1999.777346" @default.
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