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- W2149207622 abstract "Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter- and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu/SiO2 interconnection structures. After a review of the TiN-CVD performance as a diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu/TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/Cu-CVD process integration." @default.
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- W2149207622 date "2000-01-01" @default.
- W2149207622 modified "2023-09-25" @default.
- W2149207622 title "TiN-CVD process optimization for integration with Cu-CVD" @default.
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- W2149207622 doi "https://doi.org/10.1016/s0167-9317(99)00304-4" @default.
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