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- W2149211345 abstract "It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method." @default.
- W2149211345 created "2016-06-24" @default.
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- W2149211345 date "2003-10-31" @default.
- W2149211345 modified "2023-09-24" @default.
- W2149211345 title "BIST-aided scan test - a new method for test cost reduction" @default.
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- W2149211345 doi "https://doi.org/10.1109/vtest.2003.1197675" @default.
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