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- W2149363923 abstract "Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is required. The access to remote resources located on another chip needs to be relayed via gateways involving gateways between on-chip and off-chip networks (i.e., vertical integration) and gateways between different types of off-chip networks (i.e., horizontal integration). This paper introduces a system model with gateways for end-to-end channels over hierarchical, heterogeneous and mixed-criticality networks. We focus on the timing of end-to-end channels, as well as the interoperability across gateways." @default.
- W2149363923 created "2016-06-24" @default.
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- W2149363923 date "2014-08-01" @default.
- W2149363923 modified "2023-09-26" @default.
- W2149363923 title "End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips" @default.
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- W2149363923 doi "https://doi.org/10.1109/dsd.2014.34" @default.
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