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- W2149737568 abstract "This paper describes an efficient DES implementation that encrypts a 64-bit plain text block in 8 clock cycles. The 8 cycle processing latency optimizes the throughput of a pipelined DES system, where a byte-wide bus is used. Also, by decreasing the system clock frequency by a factor of 2, the switching power consumption is reduced compared to the conventional implementations. Our approach is based on the time multiplexed cipher function that requires only one copy of S-Box realization unlike other 8-cycle implementations." @default.
- W2149737568 created "2016-06-24" @default.
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- W2149737568 date "2002-11-11" @default.
- W2149737568 modified "2023-09-26" @default.
- W2149737568 title "Efficient 8-cycle DES implementation" @default.
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- W2149737568 doi "https://doi.org/10.1109/apasic.2000.896937" @default.
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