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W2149803539 abstract "For the first time we report a high performance embedded DRAM prototype fabricated in a 3D stackable 32nm High-K/Metal Gate technology with copper through-silicon vias. Post through-via processing functional test demonstrates that <1.5ns latency and 500MHz operation are preserved." @default.
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W2149803539 date "2011-06-15" @default.
W2149803539 modified "2023-09-27" @default.
W2149803539 title "3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype" @default.
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