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- W2149949638 abstract "Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with scope and zone, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LSI's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics." @default.
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- W2149949638 date "1986-07-02" @default.
- W2149949638 modified "2023-09-24" @default.
- W2149949638 title "Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's" @default.
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