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- W2149987122 abstract "The paper presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The massively parallel proposed execution core will yield high throughput for multimedia and image processing DSP applications." @default.
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- W2149987122 date "2003-06-25" @default.
- W2149987122 modified "2023-09-23" @default.
- W2149987122 title "Reconfigurable execution core for high performance DSP applications" @default.
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- W2149987122 doi "https://doi.org/10.1109/apccas.2002.1115323" @default.
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