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- W2150129170 abstract "In this work we have developed an accurate model of total leakage in a transistor stack based on the compact model of gate, subthreshold and band-to-band-tunneling leakage. Using this model, we have analyzed the opportunities for overall stand-by leakage reduction in scaled devices using transistor stacking and proved that the best input vector that minimize overall leakage depends on the relative magnitude of the different leakage components. A novel stacking technique based on the ratio of the different leakage components is proposed and its effectiveness in total leakage reduction in transistor stack and logic gate is analyzed." @default.
- W2150129170 created "2016-06-24" @default.
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- W2150129170 date "2004-03-02" @default.
- W2150129170 modified "2023-09-25" @default.
- W2150129170 title "Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits" @default.
- W2150129170 cites W1661368752 @default.
- W2150129170 cites W2157539904 @default.
- W2150129170 doi "https://doi.org/10.1109/vlsic.2003.1221159" @default.
- W2150129170 hasPublicationYear "2004" @default.
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