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- W2150911183 abstract "We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic booth logic is designed for scalability and with noise, leakage, and pulse width variation tolerance. Static partial product compression is implemented with replicated bits for performance. The design supports fine-grained clock gating domains for active power reduction." @default.
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- W2150911183 date "2005-01-01" @default.
- W2150911183 modified "2023-09-24" @default.
- W2150911183 title "The design and implementation of double-precision multiplier in a first-generation CELL processor" @default.
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- W2150911183 doi "https://doi.org/10.1109/icicdt.2005.1502577" @default.
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