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- W2151042572 abstract "This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit's noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit's parameters and selected performance metrics is also highlighted." @default.
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- W2151042572 date "2009-01-01" @default.
- W2151042572 modified "2023-09-22" @default.
- W2151042572 title "A Study on CMOS Time Uncertainty with Technology Scaling" @default.
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- W2151042572 doi "https://doi.org/10.1007/978-3-540-95948-9_15" @default.
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