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• W2151055504 abstract "We have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study." @default.
• W2151055504 created "2016-06-24" @default.
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• W2151055504 date "2006-02-01" @default.
• W2151055504 modified "2023-10-14" @default.
• W2151055504 title "Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling" @default.
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• W2151055504 doi "https://doi.org/10.1109/tc.2006.29" @default.
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