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- W2151244776 abstract "Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area." @default.
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- W2151244776 date "2008-01-01" @default.
- W2151244776 modified "2023-10-14" @default.
- W2151244776 title "Optimizing wirelength and routability by searching alternative packings in floorplanning" @default.
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- W2151244776 doi "https://doi.org/10.1145/1297666.1297687" @default.
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