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- W2151254616 abstract "The authors present novel circuits for residue arithmetic, which have been configured to form a 3*3 finite impulse response (FIR) filter with programmable coefficients. The filter has a pipelined architecture and includes testability in the form of scan path. Area efficient circuits for residue adders, subtractors, and binary-to-residue converters have been designed. An encoding scheme has been used to reduce the residue multiplier area. A tree architecture for residue-to-binary conversion has been developed. The filter is timed with a two-phase clock, which has an estimated frequency of 15 MHz. >" @default.
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- W2151254616 date "2002-12-04" @default.
- W2151254616 modified "2023-09-25" @default.
- W2151254616 title "A single-chip pipelined 2-D FIR filter using residue arithmetic" @default.
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- W2151254616 doi "https://doi.org/10.1109/naecon.1990.112748" @default.
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