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- W2151322556 abstract "This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8×8 multiplier design is reduced by more than 13.8% compared to prior designs." @default.
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- W2151322556 date "2008-05-01" @default.
- W2151322556 modified "2023-10-18" @default.
- W2151322556 title "A power-aware 2-dimensional bypassing multiplier using cell-based design flow" @default.
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- W2151322556 doi "https://doi.org/10.1109/iscas.2008.4542173" @default.
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