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- W2152507675 abstract "Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. The paper reports results showing how the proposed method can be effectively used to analyze complex designs." @default.
- W2152507675 created "2016-06-24" @default.
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- W2152507675 date "2004-03-02" @default.
- W2152507675 modified "2023-09-27" @default.
- W2152507675 title "Accurate and efficient analysis of single event transients in VLSI circuits" @default.
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- W2152507675 doi "https://doi.org/10.1109/olt.2003.1214374" @default.
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