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- W2152857845 abstract "Efficient design of large multiprocessor embedded systems requires fast, early performance modeling techniques. Native co-simulation has been proposed as a fast solution for evaluating systems in early design steps. Annotated SW execution can be performed in conjunction with a virtual model of the HW platform to generate a complete system simulation. To obtain sufficiently accurate performance estimations, the effect of all the system components, as processor caches, must be considered. ISS-based cache models slow down the simulation speed, greatly reducing the efficiency of native-based co-simulations. To solve the problem, cache modeling techniques for fast native co-simulation have been proposed, but only considering instruction-caches. In this paper, a fast technique for datacache modeling is presented, together with the instrumentation required for its application in native execution. The model allows the designer to obtain cache hit/miss rate estimations with a speed-up of two orders of magnitude with respect to ISS. Miss rate estimation error remains below 5% for representative examples." @default.
- W2152857845 created "2016-06-24" @default.
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- W2152857845 date "2011-01-25" @default.
- W2152857845 modified "2023-10-03" @default.
- W2152857845 title "Fast data-cache modeling for native co-simulation" @default.
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- W2152857845 doi "https://doi.org/10.5555/1950815.1950905" @default.
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