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• W2153302213 abstract "<para xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns. </para>" @default.
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• W2153302213 date "2008-11-01" @default.
• W2153302213 modified "2023-10-03" @default.
• W2153302213 title "FPGA-Based Digital Pulsewidth Modulator With Time Resolution Under 2 ns" @default.
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• W2153302213 doi "https://doi.org/10.1109/tpel.2008.2005370" @default.
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