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- W215355005 abstract "As improvements in integrated circuit (IC) processing technology continue to reduce both defect density and minimum feature size, increasingly complex chips are being planned, designed, and fabricated. With this increase in complexity, there comes an even greater increase in potential testing problems: a very large scale integrated (VLSI) circuit can have several internal circuit nodes that cannot be directly controlled or observed from the chip's input/output pins. The task of verifying that there are no faults hidden deep inside a VLSI circuit can be formidable, and the time and effort spent on testing problems can add significantly to the cost of IC production. This chapter discusses two broad goals of IC testing, namely, design verification and screening. Design-for-testability (DFT) techniques attempt to reduce the high cost in time and effort required to generate test vector sequences for VLSI circuits. The identification of faulty chips in the field can also be greatly simplified if the chips are designed for testability. In deciding what DFT technique to use for a given circuit, one must weigh the advantages of simpler test vector generation, higher fault coverage, and possibly reduced test application time against the disadvantages. No DFT technique is best for all situations. Once a DFT technique has been chosen for a given circuit, it is usually best to apply it consistently throughout the design cycle, from inception to completion, and not merely incorporate it into the circuit as an afterthought. Regardless of the DFT technique incorporated in a circuit and of how thoroughly the circuit is tested, the VLSI testing problem always involves some degree of uncertainty. A production fault in a VLSI circuit may go unnoticed, until it is uncovered in the field, months or years later." @default.
- W215355005 created "2016-06-24" @default.
- W215355005 creator A5065687276 @default.
- W215355005 date "1986-01-01" @default.
- W215355005 modified "2023-09-27" @default.
- W215355005 title "VLSI Design for Testability" @default.
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- W215355005 doi "https://doi.org/10.1016/b978-0-12-234114-4.50007-5" @default.
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