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- W2153564843 abstract "To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a 0.5-mum 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5 V to 16.2 V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit." @default.
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- W2153564843 date "2009-07-01" @default.
- W2153564843 modified "2023-09-23" @default.
- W2153564843 title "Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure" @default.
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- W2153564843 doi "https://doi.org/10.1109/ipfa.2009.5232701" @default.
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