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• W2153587887 abstract "Total on-chip interconnect length has been increasing exponentially with technology scaling. Consequently, interconnect-driven design is an emerging trend in state-of-the-art integrated circuits. Cu-based interconnect technology is expected to meet some of the challenges of technology scaling. However, Cu interconnects still pose a reliability concern due to electromigration-induced failure over time. The major contribution of this thesis is a new reliability CAD tool, SysRel, for thermal-aware reliability analysis with either Al or Cu metallization technology in conventional and three-dimensional integrated circuits. An interconnect tree is the fundamental reliability unit for circuit-level reliability assessments for metallization schemes with fully-blocking boundaries at the vias. When vias do not block electromigration as indicated in some Cu experimental studies, multiple trees linked by a non-blocking via are merged to create a single fundamental reliability unit. SysRel utilizes a tree-based hierarchical analysis that sufficiently captures the differences between electromigration behavior in Al and Cu metallizations. The hierarchical flow first identifies electromigration-critical nets or “mortal” trees, applies a default model to estimate the lifetimes of individual trees, and then produces a set of full-chip reliability metrics based on stochastic analysis using the desired lifetime of the circuit. We have exercised SysRel to compare layout-specific reliability with Cu and Al metallizations in various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. The required improvement will increase as low-k dielectric materials are introduced and liner thicknesses are reduced in future. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)" @default.
• W2153587887 created "2016-06-24" @default.
• W2153587887 creator A5025791255 @default.
• W2153587887 creator A5026389537 @default.
• W2153587887 creator A5061147380 @default.
• W2153587887 date "2004-01-01" @default.
• W2153587887 modified "2023-09-27" @default.
• W2153587887 title "Design tool and methodologies for interconnect reliability analysis in integrated circuits" @default.
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• W2153587887 hasPublicationYear "2004" @default.
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