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- W2153753826 abstract "Power consumption and heat generation in CMOS-based ICs are the dominating factors affecting the system's performance and reliability. Many power reduction techniques, e.g., supply voltage scaling, implementing smaller transistors, limiting switching activity, are well known in public. Supply and threshold voltage scaling is among one of the most efficient methods for reducing power. In addition, process technology designed with transistors optimized for subthreshold operation is a more fundamental path to conserve the low power characteristic of the system. To demonstrate the significance of the process, a series of digital circuits were fabricated using MIT Lincoln Lab's 90nm XLP FDSOI CMOS process with novel transistor technology optimized for 300 mV supply voltage. The circuits include synchronous ring oscillator, synchronous FIR filter, asynchronous ring oscillator, asynchronous FIR filter, and homogeneous parallel asynchronous platform." @default.
- W2153753826 created "2016-06-24" @default.
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- W2153753826 date "2015-10-01" @default.
- W2153753826 modified "2023-09-24" @default.
- W2153753826 title "Asynchronous and synchronous designs for low-power FDSOI CMOS process optimized for subthreshold operation at 0.3V V<inf>DD</inf>" @default.
- W2153753826 cites W2019714160 @default.
- W2153753826 doi "https://doi.org/10.1109/s3s.2015.7333511" @default.
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