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- W2153942016 abstract "The viability of projections for a 1994 CMOS logic chip having 3*10/sup 5/ transistors/cm/sup 2/, 20-W/cm/sup 2/ power dissipation, and 600-MHz clock frequency is assessed with respect to power distribution, signal transmission, and off-chip connections. It is found that current silicon technologies, systematically scaled to 0.25- mu m feature size, can achieve complexities of around 2*10/sup 6/ transistors/cm/sup 2/, 10-W/cm/sup 2/ power dissipation, and 150-MHz clock frequency. Projected functional throughput rates of 5*10/sup 13/-gate Hz/cm/sup 2/ are inconsistent with these parameters by more than an order of magnitude. Supplying the chips with power at acceptable Delta I noise will pose the most formidable design challenges. >" @default.
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- W2153942016 date "2003-01-06" @default.
- W2153942016 modified "2023-09-23" @default.
- W2153942016 title "Challenges of a vintage 1994 CMOS logic chip" @default.
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- W2153942016 doi "https://doi.org/10.1109/cicc.1988.20933" @default.
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