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• W2154337568 abstract "A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor." @default.
• W2154337568 created "2016-06-24" @default.
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• W2154337568 date "2014-05-01" @default.
• W2154337568 modified "2023-09-27" @default.
• W2154337568 title "A resilient 3-D stacked multicore processor fabricated using die-level 3-D integration and backside TSV technologies" @default.
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• W2154337568 doi "https://doi.org/10.1109/ectc.2014.6897303" @default.
• W2154337568 hasPublicationYear "2014" @default.
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