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- W2154673851 abstract "In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to classical CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700muW respectively when synthesized in 0.18mum CMOS library which shows its effectiveness as a low-area low-power processor." @default.
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- W2154673851 date "2007-05-01" @default.
- W2154673851 modified "2023-10-16" @default.
- W2154673851 title "On the Hardware Reduction of z-Datapath of Vectoring CORDIC" @default.
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- W2154673851 doi "https://doi.org/10.1109/iscas.2007.377978" @default.
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