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• W2154764836 abstract "The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. Before verification is applied to each individual module, irrelevant information to the behavior of the selected module is abstracted away. This approach converts a verification problem with big exponential complexity to a set of subproblems, each with small exponential complexity. Experimental results are promising in that they indicate that our approach has the potential of completing much faster while using less memory than traditional flat analysis." @default.
• W2154764836 created "2016-06-24" @default.
• W2154764836 creator A5005072374 @default.
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• W2154764836 date "2003-09-01" @default.
• W2154764836 modified "2023-09-25" @default.
• W2154764836 title "Modular verification of timed circuits using automatic abstraction" @default.
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• W2154764836 doi "https://doi.org/10.1109/tcad.2003.816214" @default.
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