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• W2154911519 abstract "This paper proposes a unified delay test architecture, in which the design resources for on-line delay fault detection can be reused to support off-line delay testing. A stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. A global error generator, which is shared among stability checkers, can produce a global error signal from individual stability checkers to indicate whether a delay fault appears. A local scan enable generator is incorporated into the scan chain to support scan-based off-line delay testing. Experimental results are presented to validate the effectiveness of the proposed approach." @default.
• W2154911519 created "2016-06-24" @default.
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• W2154911519 date "2011-05-01" @default.
• W2154911519 modified "2023-09-27" @default.
• W2154911519 title "A unified test architecture for on-line and off-line delay fault detections" @default.
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• W2154911519 doi "https://doi.org/10.1109/vts.2011.5783733" @default.
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