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- W2154967995 abstract "A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f/sub 0/ is first-order independent of V/sub DD/, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8/spl mu/m CMOS process, occupying an area of 0.15mm/sup 2/. Nominal f/sub 0/ is 1 MHz, with K/sub VCO/=8.4KHz/mV. Measured sensitivity to V/sub DD/ is below 2.17, while phase noise is -86dBc at 100 kHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35/spl mu/m CMOS process and V/sub DD/=3.3V, with a linear frequency-span of 13.2 MHz-61.5 MHz." @default.
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- W2154967995 date "2004-09-07" @default.
- W2154967995 modified "2023-10-01" @default.
- W2154967995 title "A low-voltage low sensitivity sinusoidal VCO for DPLL realizations" @default.
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- W2154967995 doi "https://doi.org/10.1109/iscas.2004.1328313" @default.
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