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- W2155068144 abstract "Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance." @default.
- W2155068144 created "2016-06-24" @default.
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- W2155068144 date "2002-11-19" @default.
- W2155068144 modified "2023-09-27" @default.
- W2155068144 title "Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure" @default.
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- W2155068144 doi "https://doi.org/10.1109/soi.1995.526479" @default.
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