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- W2155369439 abstract "High-speed and low-power operation of a 1:4 demultiplexer IC with a multi-phase clock (MPC) architecture is reported. The architecture features four parallel latch lines and a toggle flip-flop (TFF) that generates a four-phase clock. The IC, which was fabricated using InP HEMTs, exhibited 50-Gbit/s error-free operation with a power consumption of 1.42 W. Compared to a conventional tree-type InP HEMT 1:4 demultiplexer IC, the IC with the MPC architecture operates at the same operating speed with only one-quarter the power consumption." @default.
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- W2155369439 date "2003-08-27" @default.
- W2155369439 modified "2023-09-26" @default.
- W2155369439 title "1.4-W 50-Gbit/s InP HEMT 1:4 demultiplexer IC with a multi-phase clock architecture" @default.
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- W2155369439 doi "https://doi.org/10.1109/mwsym.2003.1212579" @default.
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