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- W2155542402 abstract "The design of a 6.8*6-cm wafer-scale integration (WSI) chip for matrix-matrix multiplication, the layout, and its verification hierarchy are described. The chip is designed in a defect-tolerant style. Whole wafer lithography resulting in 2- mu m effective design rules was chosen because of reduced costs of masks. >" @default.
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- W2155542402 date "2003-01-07" @default.
- W2155542402 modified "2023-09-24" @default.
- W2155542402 title "On the design of a selftesting WSI multiplier array" @default.
- W2155542402 doi "https://doi.org/10.1109/wafer.1989.47561" @default.
- W2155542402 hasPublicationYear "2003" @default.
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