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• W2155585465 abstract "Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. WLP is the upcoming future packaging technology. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for integration of functionality. The increasing demand for new and more advanced electronic products with smaller form factor and superior functionality and performance, is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for Fan-in (FI) WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires Fan-out (FO) packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the second level interconnect. eWLB is a type of FO-WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. This paper will highlight some of the recent characterization works of thermal and electrical performance of eWLB package. The performance compared with other packaging format, i.e. FI-WLP and other array packages is discussed with simulation data. Based on computational fluidic dynamics (CFD) simulation, Θja of eWLB package is calculated and it was comparable with FI-WLP's. Thermal characterization activity is carried out to investigate the effect on eWLB configuration with power loading. Thin film based passives on the FO area (mold material) of the eWLB is also analyzed during electrical characterization. Due to the low-loss property of the mold material, plated Cu inductors showed high quality-factor (Q) performance. The mold material in FO area is not only used as a supporting substrate, but also serves as the package substrate, which allows the high-Q inductors to be implemented with other RF chips in one single package. In addition, parasitic (RLC) electrical performance results will be presented in this paper too." @default.
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• W2155585465 date "2010-01-01" @default.
• W2155585465 modified "2023-09-26" @default.
• W2155585465 title "Thermal and electrical characterization of eWLB (embedded Wafer Level BGA)" @default.
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• W2155585465 doi "https://doi.org/10.1109/ectc.2010.5490832" @default.
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