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• W2155707315 abstract "Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>RLC</i> parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>RLC</i> model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits." @default.
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• W2155707315 date "2010-01-01" @default.
• W2155707315 modified "2023-10-15" @default.
• W2155707315 title "Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs" @default.
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• W2155707315 doi "https://doi.org/10.1109/ted.2009.2034508" @default.
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