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- W2156412034 abstract "Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow the test of multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT in order to maximize the test throughput for a given SOC and ATE. The onchip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC test benchmarks." @default.
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- W2156412034 date "2005-04-01" @default.
- W2156412034 modified "2023-10-01" @default.
- W2156412034 title "On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips" @default.
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- W2156412034 doi "https://doi.org/10.1109/date.2005.231" @default.
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