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• W2156416222 abstract "To achieve disturb-free writing, we proposed a new writing operation for ferroelectric-gate field-effect transistor memories with intermediate electrodes. The writing voltages V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> applied to the wordlines for Pr <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> and Pr <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>0</sup> memory states are the same pulse magnitudes, which consist of V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> followed by V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-</sup> , whereas the bias timings of the bitline voltages differ from each other. The bitline voltage for the Pr <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> memory state is set high when V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> is set V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> , and it is set to low by the time when V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> is changed to V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-</sup> . On the other hand, the bitline voltage for the Pr <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>0</sup> memory state is set high until the whole writing pulse of (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>+</sup> + V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>W</sub> <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-</sup> ) is finished. This is verified experimentally using a discrete circuit, which showed that the new writing operation achieves disturb-free writing. The memory consists of two transistors for data writing and reading. With the obtained experimental results, we discuss the possibilities of high integration of this memory as well as low reading voltage." @default.
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• W2156416222 date "2009-12-01" @default.
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• W2156416222 title "Disturb-Free Writing Operation for Ferroelectric-Gate Field-Effect Transistor Memories With Intermediate Electrodes" @default.
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• W2156416222 doi "https://doi.org/10.1109/ted.2009.2032744" @default.
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