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• W2156576534 abstract "What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects." @default.
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• W2156576534 date "2009-05-01" @default.
• W2156576534 modified "2023-10-16" @default.
• W2156576534 title "Is 25 Gb/s On-Board Signaling Viable?" @default.
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• W2156576534 doi "https://doi.org/10.1109/tadvp.2008.2011138" @default.
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