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- W2157245959 abstract "Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design, is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>INT</i> Manchester adder can achieve 1.66times average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>(SNR)</i> environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-mu m process." @default.
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- W2157245959 date "2008-12-01" @default.
- W2157245959 modified "2023-10-17" @default.
- W2157245959 title "Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits" @default.
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- W2157245959 doi "https://doi.org/10.1109/tvlsi.2008.2001563" @default.
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