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• W2157287967 startingPage "1769" @default.
• W2157287967 abstract "A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-/spl mu/m CMOS, the 16-mm/sup 2/ ADC dissipates 850 mW." @default.
• W2157287967 created "2016-06-24" @default.
• W2157287967 creator A5028638391 @default.
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• W2157287967 date "2000-12-01" @default.
• W2157287967 modified "2023-10-10" @default.
• W2157287967 title "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR" @default.
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• W2157287967 doi "https://doi.org/10.1109/4.890290" @default.
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