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- W2158025890 abstract "In this paper we study the problem of selecting a set of paths to optimize the performance of a combinational circuit. We assume that gate resizing and buffer insertion are the two possible optimizing techniques used to reduce the delay of a circuit; that is, during the optimization process the topol- ogy of a circuit remains the same and the lead/gate delays are reduced. The objective of the path selection problem is to select as small as possible a set of paths to ease the optimization pro- cess. However, we also want to guarantee the delay of the cir- cuit is no longer than a given threshold T if the delays of all the selected paths are shortened to no longer than T. In this paper we have shown that the path selection is different from path sensitization. We first proposed an input vector-oriented path selection algorithm. Due to the fact that the input vector-ori- ented algorithm may be infeasible for complex circuits with many primary inputs, we also designed and developed a path- oriented algorithm. We have implemented the path-oriented al- gorithm. The experimental results on ISCASSS benchmark cir- cuits show a potentially big improvement for optimization pro- cess. For some circuits, less than 10% of the long paths need to be shortened." @default.
- W2158025890 created "2016-06-24" @default.
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- W2158025890 date "1991-01-01" @default.
- W2158025890 modified "2023-09-24" @default.
- W2158025890 title "Critical path selection for performance optimization" @default.
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- W2158025890 doi "https://doi.org/10.1145/127601.127730" @default.
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