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- W2158464772 abstract "In a gate-level description of a finite state machine (fsm), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples." @default.
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- W2158464772 date "1996-11-10" @default.
- W2158464772 modified "2023-09-24" @default.
- W2158464772 title "Latch optimization in circuits generated from high-level descriptions" @default.
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- W2158464772 doi "https://doi.org/10.5555/244522.244847" @default.
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