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- W2159444986 abstract "In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130 nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%." @default.
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- W2159444986 date "2007-12-01" @default.
- W2159444986 modified "2023-09-26" @default.
- W2159444986 title "A Controllable low-power dual-port embedded SRAM for DSP processor" @default.
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- W2159444986 doi "https://doi.org/10.1109/mtdt.2007.4547610" @default.
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