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- W2159701297 abstract "Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multi-standard radio baseband processors. A demonstrator chip for 802.11 a/b/g physical layer baseband processing was manufactured in 0.18 /spl mu/m CMOS. The silicon area is 2.9 mm/sup 2/, including all memories." @default.
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- W2159701297 date "2005-01-01" @default.
- W2159701297 modified "2023-09-22" @default.
- W2159701297 title "A low area and low power programmable baseband processor architecture" @default.
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- W2159701297 doi "https://doi.org/10.1109/iwsoc.2005.14" @default.
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