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• W2160139157 abstract "Abstract NULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification." @default.
• W2160139157 created "2016-06-24" @default.
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• W2160139157 date "2011-01-01" @default.
• W2160139157 modified "2023-09-30" @default.
• W2160139157 title "Modeling and Verification of NCL Circuits Using PAT" @default.
• W2160139157 cites W2110425399 @default.
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• W2160139157 doi "https://doi.org/10.1016/j.proeng.2011.08.639" @default.
• W2160139157 hasPublicationYear "2011" @default.
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