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• W2160280813 abstract "Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV solver designed for FPGAs (SSF). Besides high computational throughput, system performance is optimized by reducing initialization time and overheads, minimizing and overlapping I/O operations, and increasing scalability. SSF accepts any matrix size and can be easily adapted to different data formats. SSF minimizes the control logic by taking advantage of the data flow via an innovative accumulation circuit which uses pipelined floating point adders. Compared to optimized software codes on a Pentium 4 microprocessor, our design achieves up to 20x speedup." @default.
• W2160280813 created "2016-06-24" @default.
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• W2160280813 date "2007-04-01" @default.
• W2160280813 modified "2023-09-23" @default.
• W2160280813 title "Sparse Matrix-Vector Multiplication Design on FPGAs" @default.
• W2160280813 cites W1981252059 @default.
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• W2160280813 doi "https://doi.org/10.1109/fccm.2007.56" @default.
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