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• W2160331356 abstract "To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA. On the other hand, current FPGA logic cells have already been enhanced with carry chains to improve arithmetic functionality, for example, to realize fast ternary carry-propagate addition. The contribution of this article is a new FPGA logic cell that is specialized to help realize efficient compressor trees on FPGAs. The new FPGA logic cell has two variants that can respectively be configured as a 6:2 or a 7:2 compressor using additional carry chains that, coupled with lookup tables, provide the necessary functionality. Experiments show that the use of these modified logic cells significantly reduces the delay of compressor trees synthesized on FPGAs compared to state-of-the-art synthesis techniques, with a moderate increase in area and power consumption." @default.
• W2160331356 created "2016-06-24" @default.
• W2160331356 creator A5011244614 @default.
• W2160331356 creator A5020575991 @default.
• W2160331356 creator A5034231760 @default.
• W2160331356 date "2009-09-01" @default.
• W2160331356 modified "2023-10-01" @default.
• W2160331356 title "An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor" @default.
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• W2160331356 doi "https://doi.org/10.1145/1575774.1575778" @default.
• W2160331356 hasPublicationYear "2009" @default.
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