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• W2160487048 abstract "The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are the solution for a high-resolution ADC having tolerance of analog component errors. Oversampling reduces input temporal noise as well as the quantization error of the ADC itself [1]. However, an I-ΔΣ ADC is also classified as a slow ADC because it requires exponential conversion time to get higher bit resolution. To reduce conversion time, there are two alternative methods: 1) higher-order modulation, and 2) two-step conversion such as an extended-counting technique [2]. In this paper, the extended-counting (EC) method is used since a high-order structure requires more complex hardware and greater power consumption [1,2]. For a general two-step ADC, coarse conversion restricts the total ADC resolution since it determines accuracy of the residue. However, an EC ADC overcomes the accuracy limitation, since the I-ΔΣ can improve its precision through oversampling. Moreover, oversampling also suppresses the noise of the pixel's source follower. Our 14b EC ADC is a blend of a 1 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>st</sup> -order I-ΔΣ ADC and a cyclic ADC to simultaneously get high resolution and high speed." @default.
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• W2160487048 date "2012-02-01" @default.
• W2160487048 modified "2023-10-10" @default.
• W2160487048 title "A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor" @default.
• W2160487048 cites W2018657325 @default.
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• W2160487048 doi "https://doi.org/10.1109/isscc.2012.6177060" @default.
• W2160487048 hasPublicationYear "2012" @default.
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