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• W2160668294 abstract "Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection networks plays a critical role in shared memory MPSoC designs. In this paper, we propose a directory-cache embedded switch architecture with distributed shared cache and distributed shared memory. It is able to reduce the number of home node cache accesses, which results in a reduction in the inter-cache transfer time and the total execution time. Simulation results verify that the proposed methodology can improve performance substantially over a design in which directory caches are not embedded in the switches." @default.
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• W2160668294 date "2006-09-22" @default.
• W2160668294 modified "2023-09-24" @default.
• W2160668294 title "DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs" @default.
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• W2160668294 doi "https://doi.org/10.1109/iscas.2006.1692751" @default.
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