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- W2161668815 abstract "Presents hardware and software techniques for configuring a wafer scale 2D array. A switching network independent of the processing elements (PEs) has been designed and implemented. Two algorithms find and program an optimized target array in a reversible or irreversible manner. This paper is based on a wafer scale design for low-level image processing.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2161668815 date "1993-01-01" @default.
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- W2161668815 title "A real experience on configuring a wafer scale 2D array of monobit processors" @default.
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- W2161668815 doi "https://doi.org/10.1109/33.257871" @default.
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