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• W2161891759 abstract "Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was proposed. Without violating the system error-rate constraint specified by the user, this methodology identifies a set of faults that can be ignored during testing, thereby leading to a significant improvement in yield. However, usually the patterns detecting all of the unacceptable faults also detect a large number of acceptable faults, resulting in a degradation in achievable yield improvement. In this paper, the authors first provide a probabilistic analysis of this problem and show that a conventional ATPG procedure cannot adequately address this problem. The authors then present a novel test pattern selection procedure and an output masking technique to deal with this problem. The selection process generates a test set aimed to detect all unacceptable faults but as few acceptable faults as possible. The masking technique then examines the generated test patterns and identifies a list of output lines that can be masked (not observed) during testing so as to further avoid the detection of acceptable faults. Experimental results show that by employing the proposed techniques, only a small number of acceptable faults are still detected. In many cases the actual yield improvement approaches the optimal value that can be achieved" @default.
• W2161891759 created "2016-06-24" @default.
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• W2161891759 date "2007-04-16" @default.
• W2161891759 modified "2023-09-23" @default.
• W2161891759 title "Reduction of detected acceptable faults for yield improvement via error-tolerance" @default.
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• W2161891759 doi "https://doi.org/10.5555/1266366.1266717" @default.
• W2161891759 hasPublicationYear "2007" @default.
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