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- W2162282190 abstract "A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference." @default.
- W2162282190 created "2016-06-24" @default.
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- W2162282190 date "2008-09-30" @default.
- W2162282190 modified "2023-09-27" @default.
- W2162282190 title "A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter" @default.
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- W2162282190 doi "https://doi.org/10.5573/jsts.2008.8.3.193" @default.
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